1. Field of the Invention
The present invention relates generally to damascene methods for forming microelectronic fabrications. More particularly, the present invention relates to damascene methods for forming, with enhanced performance and enhanced reliability, microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common in the art of microelectronic fabrication to employ interposed between the patterns of patterned microelectronic conductor layers when fabricating microelectronic fabrications microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials. Such comparatively low dielectric constant dielectric materials generally have dielectric constants in a range of from about 1.5 to less than about 4.0. For comparison purposes, microelectronic dielectric layers formed within microelectronic fabrications from conventional silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials typically have comparatively high dielectric constants in a range of from greater than about 4.0 to about 8.0. Similarly, microelectronic fabrications comprising patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials are typically formed within microelectronic fabrications while employing damascene methods, including in particular dual damascene methods.
Microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials are desirable in the art of microelectronic fabrication formed interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications insofar as such microelectronic dielectric layers formed of dielectric materials having comparatively low dielectric constants provide microelectronic fabrications which may theoretically operate at higher microelectronic fabrication speeds, with attenuated patterned microelectronic conductor layer parasitic capacitance and attenuated patterned microelectronic conductor layer cross-talk.
Similarly, damascene methods are desirable in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials insofar as damascene methods are comparatively simple fabrication methods which may often be employed to fabricate microelectronic structures which are not otherwise practicably accessible in the art of microelectronic fabrication.
While damascene methods are thus desirable in the art of microelectronic fabrication for forming microelectronic fabrications comprising patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, damascene methods are nonetheless not entirely without problems in the art of microelectronic fabrication for forming microelectronic fabrications comprising patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials. In that regard, while damascene methods are generally successful for forming microelectronic fabrications comprising patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, such damascene methods are often difficult to employ for forming, with enhanced performance and enhanced reliability, microelectronic fabrications comprising patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials.
It is thus desirable in the art of microelectronic fabrication to provide damascene methods which may be employed for forming, with enhanced performance and enhanced reliability, microelectronic fabrications comprising patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials.
It is towards the foregoing object that the present invention is directed.
Various damascene methods have been disclosed in the art of microelectronic fabrication for forming damascene structures with desirable properties.
Included among the damascene methods, but not limited among the damascene methods, are damascene methods disclosed within: (1) Huang, in U.S. Pat. No. 6,177,364 (a hydrogen/nitrogen plasma treatment method for treating exposed sidewall surfaces of a pair of fluorosilicate glass (FSG) inter-metal dielectric (IMD) layers within a dual damascene aperture such as to passivate the exposed sidewall surfaces with respect to mobile fluorine diffusion therefrom within the dual damascene aperture); and (2) Yu et al., in U.S. Pat. No. 6,187,663 (a damascene method for forming a damascene structure with enhanced performance by forming the damascene structure with an inter-metal dielectric (IMD) layer comprising a hydrogen silsesquioxane (HSQ) based dielectric layer having formed thereupon a fluorosilicate glass (FSG) dielectric layer).
Desirable in the art of microelectronic fabrication are additional damascene methods and materials which may be employed for providing microelectronic fabrications comprising patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, with enhanced performance and enhanced reliability.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a damascene method for forming a microelectronic fabrication comprising a patterned microelectronic conductor layer having formed interposed between its patterns a microelectronic dielectric layer formed of a comparatively low dielectric constant dielectric material.
A second object of the present invention is to provide a damascene method in accord with the first object of the present invention, wherein the microelectronic fabrication is formed with enhanced performance and enhanced reliability.
A third object of the present invention is to provide a damascene method in accord with the first object of the present invention and the second object of the present invention, wherein the damascene method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a microelectronic fabrication.
To practice the method of the present invention, there is first provided a substrate having formed therein a contact region. There is then formed over the substrate an etch stop layer comprising: (1) a first etch stop sub-layer formed from a comparatively low dielectric constant dielectric material; and (2) a second etch stop sub-layer formed upon the first etch stop sub-layer and formed from a comparatively high dielectric constant dielectric material. There is then formed over the etch stop layer an inter-metal dielectric layer having formed thereupon an anti-reflective coating layer. There is then formed, exposed and developed upon the anti-reflective coating layer a photoresist layer to form a patterned photoresist layer formed upon the anti-reflective coating layer. There is then patterned the anti-reflective coating layer and the inter-metal dielectric layer at least in part while employing the patterned photoresist layer as a mask to form a patterned anti-reflective coating layer and a patterned inter-metal dielectric layer which define an aperture which reaches the etch stop layer at a location above the contact region. There is then stripped the patterned photoresist layer from the patterned anti-reflective coating layer. Finally, there is then etched simultaneously the patterned anti-reflective coating layer and the etch stop layer to expose a top surface of the patterned inter-metal dielectric layer and to form from the aperture an extended aperture which exposes a top surface of the contact region.
Within the present invention, there may then be formed into the extended aperture (which may comprise a damascene aperture) a patterned conductor layer, while employing a damascene method, to provide the microelectronic fabrication with enhanced performance and enhanced reliability.
There is provided by the present invention a damascene method for forming within a microelectronic fabrication a patterned microelectronic conductor layer having formed interposed between its patterns a microelectronic dielectric layer formed of a comparatively low dielectric constant dielectric material, wherein the microelectronic fabrication is formed with enhanced performance and enhanced reliability.
The present invention realizes the foregoing object by employing when fabricating the microelectronic fabrication an etch stop layer comprising: (1) a first etch stop sub-layer formed from a comparatively low dielectric constant dielectric material; and (2) a second etch stop sub-layer formed upon the first etch stop sub-layer and formed from a comparatively high dielectric constant dielectric material, where the etch stop layer in turn has formed thereover: (1) an inter-metal dielectric layer having formed thereupon; (2) an anti-reflective coating layer in turn having formed thereupon (3) a patterned photoresist layer which is employed as an etch mask for forming from the foregoing two layers a corresponding patterned inter-metal dielectric layer having formed thereupon a patterned anti-reflective coating layer. Within the present invention, after having stripped the patterned photoresist layer from the patterned anti-reflective coating layer, the patterned anti-reflective coating layer is stripped from the patterned inter-metal dielectric layer while simultaneously etching the etch stop layer to form a patterned etch stop layer which exposes a contact region within a substrate over which is formed all of the foregoing layers.
The method in accord with the present invention is readily commercially implemented.
As will be illustrated in greater detail within the context of the Description of the Preferred Embodiment, as set forth below, the method of the present invention employs methods and materials as are otherwise generally known in the art of microelectronic fabrication, but employed within the context of specific process limitations and specific materials limitations to provide the method of the present invention. Since it is thus at least in part a series of specific process limitations and specific materials limitations which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.